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Silicon Errors in Logic - System Effects

SELSE-11: The 11th Workshop on Silicon Errors in Logic - System Effects

March 31 - April 1, 2015 - Austin TX


The growing complexity and shrinking geometries of modern manufacturing technologies are making high-density, low-voltage devices increasingly susceptible to the influences of electrical noise, process variation, transistor aging, and the effects of natural radiation. The system-level impact of these errors can be far-reaching. Growing concern about intermittent errors, unstable storage cells, and the effects of aging are influencing system design and failures in memories account for a significant fraction of costly product returns. Emerging logic and memory device technologies introduce several reliability challenges that need to be addressed to make these technologies viable. Finally, reliability is a key issue for large-scale systems, such as those in data centers. The SELSE workshop provides a forum for discussion of current research and practice in system-level error management. Participants from industry and academia explore both current technologies and future research directions (including nanotechnology). SELSE is soliciting papers that address the system-level effects of errors from a variety of perspectives: architectural, logical, circuit-level, and semiconductor processes. Case studies are also solicited.

Key areas of interest are (but not limited to):

  • Technology trends and the impact on error rates.
  • New error mitigation techniques.
  • Characterizing the overhead and design complexity of error mitigation techniques.
  • Case studies describing the tradeoffs analysis for reliable systems.
  • Experimental silicon failure data.
  • System-level models: derating factors and validation of error models.
  • Error handling protocols (higher-level protocols for robust system design).
  • Characterization of reliability of systems deployed in the field and mitigation of issues.

Keynote Speakers:

Important dates: Please note that submission deadlines are earlier than for previous SELSE workshops.

  • Register to submit a paper: December 8, 2014 January 2, 2015
  • Paper submission: December 15, 2014 January 2, 2015
  • Authors notification: January 30, 2015 February 6, 2015
  • Final paper submission: February 18, 2015 February 23, 2015

Download Call for Participation in PDF

Last Updated on Wednesday, 28 January 2015 23:08

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