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Silicon Errors in Logic - System Effects

SELSE-10: The 10th IEEE Workshop on Silicon Errors in Logic - System Effects

April 1-2, 2014 - Stanford University

Stanford University

Registration is now open

Registration is available here, with early registration ending March 14, 2014. Information on transportation and local arrangements is available here.

SELSE-10 Program:

This year's SELSE workshop features three keynote talks. Bill Dally (Nvidia / Stanford University) will discuss resilience issues for ExaScale systems and some open challenges. Karl Greb (Texas Instruments) will bridge the gap between two domains by helping semiconductor developers understand how silicon errors are considered in current functional safety state-of-the-art. Finally, Tom Pawlowski (Micron) will explore error sources found in the latest generation DRAM and NAND device subsystems and discuss general principles of useful error mitigation methods.

A panel discussion with industry experts Norbert Seifert (Intel), Charles Slayman (Cisco), and Vikas Chandra (ARM) will discuss whether all reliability issues have been resolved for late CMOS technologies.

The full 2-day technical program comprised of recent research results from industrial groups and universities worldwide can be found here.


Panel Discussion:

  • All the Reliability Issues Have Been Resolved for Late CMOS Technologies

Important dates:

  • Camera-ready submission: February 28, 2014
  • Early registration deadline: March 14, 2014
  • Conference dates: April 1-2, 2014

Download Call for Participation in PDF

Last Updated on Wednesday, 12 March 2014 22:29

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