Call for Participation
Workshop on Silicon Errors in Logic – System Effects
Stanford University — April 1-2, 2014
Abstract Submission Deadline: December 13, 2013 | Paper Submission Deadline: December 20, 2013
The growing complexity and shrinking geometries of modern manufacturing technologies are making high-density, low-voltage devices increasingly susceptible to the influences of electrical noise, process variation, transistor aging, and the effects of natural radiation. The system-level impact of these errors can be far-reaching. Growing concern about intermittent errors, unstable storage cells, and the effects of aging are influencing system design and failures in memories account for a significant fraction of costly product returns. The SELSE workshop provides a forum for discussing current research and practice in system- level error management. Participants from industry and academia explore both current technologies and future research directions (including nanotechnology). SELSE is soliciting papers that address the system- level effects of errors from a variety of perspectives: architectural, logical, circuit-level, and semiconductor processes. Case studies are also solicited.
Key areas of interest are (but not limited to):
- Technology trends and the impact on error rates.
- New error mitigation techniques.
- Characterizing the overhead and design complexity of error mitigation techniques.
- Case studies describing the tradeoffs analysis for reliable systems.
- Experimental silicon failure data.
- System-level models: derating factors and validation of error models.
- Error handling protocols (higher-level protocols for robust system design).
Authors are requested to register an abstract by December 13th, 2013 and to submit their paper by December 20th 2013. Papers will be considered for both oral and poster presentation. All accepted submissions are included in the workshop proceedings. Authors will be notified by February 4th, 2014. Camera-ready papers are due on February 28th, 2014. Additional information and guidelines for submission are available at here. Submissions should be in PDF following IEEE two-column conference proceedings format that does not exceed four printed pages. Final papers may be up to six pages in length. Papers are not made available through IEEE and authors retain the copyright of their work. Authors may optionally choose to make their final papers and/or presentations available online at the workshop web site.
- Abstract submission: December 13, 2013
- Paper submission: December 20, 2013
- Authors notification: February 4, 2014
- Camera-ready submission: February 28, 2014